From unboxing to a working FPGA-connected host application, in an afternoon.
SYZYGY is the open peripheral standard that bridges the gap between bulky FMC cards and limited Pmod connectors — high pin counts and real bandwidth in a compact, low-cost, swappable form factor. Change what your Hub does without redesigning a board — plug a peripheral into any of its three ports and go.
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FrontPanel® 6
FPGA bring-up normally disappears into drivers, USB, and host integration before you write a line of your own code. FrontPanel 6 ships with every SYZYGY Hub and handles all of it — so you skip straight to the work that matters.
Talk to your hardware over USB from C++, Python, C#, and more — no driver development, no low-level USB code.
Build host-side apps fast with AI tools like Claude Code and Cursor. Connect them straight to the FPGA for read and control via natural language with an MCP server.
Build production-ready host-side applications in TypeScript/HTML — with live reload, DevTools debugging, and the full web UI toolkit.
FrontPanel 6 ships with ready-to-run examples, pre-built AXI gateware, and reference designs — load a demo and talk to the board without waiting on a Vivado build.
Included
Every Hub ships with a library of FrontPanel example apps — open one and you're reading registers, streaming data, and driving peripherals in minutes, with full source to build from.
Grab a curated bundle for a common workflow, or mix and match SYZYGY peripherals below to build your optimal kit. Every order ships with FrontPanel 6 and a USB Type-C cable.
Adapt and break out. Connect anything to the Hub.
Pixels straight into FPGA fabric, no frame grabber in between.
Capture, process, generate. Analog in, FPGA logic in the middle, analog out.
Slow-and-precise DAQ alongside a full-rate 125 MSPS signal chain.
Don’t see your exact setup? Build your own kit →
Building your own SYZYGY peripheral? Hub, breakout, pass-thru debug, and loopback test in one bundle.
Start with the Hub, then add the peripherals you need: 15% off 1 peripheral, 20% off 2, or 25% off 3 or more.
SYZYGY Hub Required
Add SYZYGY peripherals
Cables and mounting hardware don’t count toward the kit discount.
| Device | AMD Artix UltraScale+ |
| Part number | XCAU10P-1FFVB676E |
| System logic cells | 96,000 |
| CLB flip-flops | 88,000 |
| CLB LUTs | 37,000 |
| Distributed RAM | 1.0 Mib |
| Block RAM | 3.5 Mib |
| DSP slices | 400 |
| Clock management tiles | 3 |
| Host interface | USB 3.2 Gen 2 |
| Connector | USB Type-C |
| Gateware interface | AXI (AXI-Lite · AXI-Full · AXI-Stream) |
| Bandwidth | 10 Gbps (SuperSpeed) |
| Software | FrontPanel SDK |
| Memory | 1 GiB DDR4 SDRAM |
| Data width | 16-bit |
| Ports | 3 × SYZYGY Standard |
| Bank types | HP and HD |
| VIO range (SmartVIO) | 1.2 – 3.3 V |
| Power groups | 2 SYZYGY groups |
| +5 V rail | Up to 3 A |
| +3.3 V rail | Up to 3 A |
| Oscillator | 156.25 MHz LVDS |
| Frequency stability | ± 50 ppm |
| Jitter | 2.5 ps RMS |
Stability and jitter are manufacturer specifications for the oscillator component. Clock performance at the FPGA depends on the on-board signal path.
| Parameter | Min | Typ | Max | Units |
|---|---|---|---|---|
| DC input voltage | +5 | — | +15 | VDC |
| DC input ripple | — | — | 50 | mVp-p |
| USB-C power (data port) | — | — | 15 | W |
| USB-C power (power port) | — | — | 45 | W |
| Operating temperature | 0 | — | +70 | °C |
| Storage temperature | −50 | — | +100 | °C |
| Dimensions | — | 100 × 100 | — | mm |
| Weight | — | 51 | — | grams |
| Operating systems | Windows 10 / 11, macOS 11+, Ubuntu 22.04 / 24.04, Rocky Linux 9 / 10, Raspberry Pi OS |
| Languages | C / C++, Python, C#, Java, Ruby · TypeScript & HTML (Platform) |
| FPGA toolchain | AMD Vivado (7-Series and later) |
| Host software | FrontPanel SDK · FrontPanel 6 Platform |
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