Add-On Boards
Reference designs, breakout boards, and other peripherals are available for many of our FPGA modules.
Add-On Boards
Reference designs, breakout boards, and other peripherals are available for many of our FPGA modules.
Expert Challenge
Opal Kelly challenged its experts to create a useful PC-based logic analyzer using an Opal Kelly XEM3001, XEM3005, or XEM3010 (and, optionally, a BRK3005 or BRK3010 breakout board). Very few constraints were placed on the design, but generally:
Rainer Malzbender’s Logic Analyzer
Rainer was able to pull extensively from previous work and built a very functional graphical logic analyzer. He used the BRK3005 and incorporated a simple pseudo-random signal generator to exercise his logic analyzer. When male headers are installed in the BRK3005, several jumpers connect his signal generator to his logic analyzer to easily demonstrate the capabilities.
The user specifies the trigger mechanism using an intuitive 0, 1, or X (don’t care) selection next to each signal name and can even set the trigger position within the full capture buffer.
Rainer Malzbender’s Project Sources
Download ZIP (795 kiB)
Kevin Smith’s Logic Analyzer
Kevin Smith decided to use the opportunity to learn a new development environment. The Logic Analyzer in a Day project was his first attempt at C# development. His analyzer has a simple GUI with textual output of the acquired data rather than a waveform view.
Kevin’s VHDL has a few hidden gems that could prove useful to other Opal Kelly developers including extensive Python scripts for command-line build of Xilinx projects as well as a unique way to define endpoints within the FrontPanel framework.
Kevin Smith’s Project Sources
Download ZIP (536 kiB)
Klaus Zietlow’s Logic Analyzer
Klaus is a long-time user of LabVIEW for prototyping complex systems, so it was a natural choice for him to re-use some previous projects to build up his logic analyzer GUI under the demanding one-day timeline. Many Opal Kelly customers use LabVIEW with the FrontPanel SDK, so we were pleased to see an entry take this direction.
Klaus was also the only one of the three to utilize Verilog in his design.
Klaus Zietlow’s Project Sources
Download ZIP (491 kiB)
Caveats and Credits
These projects are meant as exhibition projects for both the HDL experts involved and the Opal Kelly modules. The results are not intended as full-blown bullet-proof products. A single day is barely enough to sketch out a proof-of-concept, but our experts surprised us with their results!
Thanks to the designers who took the time to work on these projects. We hope the exercise was both fun and productive!
These projects come AS-IS with no support or warranty from either Opal Kelly or the associated designers.
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