FrontPanel HDL Simulation Libraries

Opal Kelly strives to make learning and working with FrontPanel fast and easy. Our HDL Simulation Libraries are an important element of this goal.

By combining function calls in your HDL test fixture with our precompiled simulation libraries, the bridge between FrontPanel API and FrontPanel HDL modules can be simulated.

ModelSim and Aldec ActiveHDL 7.1

Xilinx distributes a free version of ModelSim XE. The FrontPanel simulation libraries have been compiled to work with this free version, in Verilog or VHDL, but also work with other releases of ModelSim (SE or PE, for example). We also have libraries available for Aldec's ActiveHDL.

Simulation Calls

For Verilog simulation test fixtures, functions and tasks are provided to mimic most of the FrontPanel API calls. For VHDL, functions and procedures perform this task.

Below, a few of the Verilog calls for a DES encryption/decryption system compare to the C++ API implementation of the same task. Note the similarity between structure and function calls. This similarity is important in order to maintain valid simulations as your design changes. It also serves to motivate the creation of test fixtures because, in many cases, there is little additional cost to doing so.